1. Field of the Invention
The present disclosure relates generally to a semiconductor memory device and, more particularly, to a nonvolatile semiconductor device containing cell strings with dummy memory cells.
2. Description of the Related Art
Nonvolatile semiconductor memory devices include both NAND type memory devices and NOR type memory devices. Both types of memory devices include memory cells. Specifically, in a NAND-type nonvolatile semiconductor memory device, pluralities of memory cells are connected in series to form cell strings. Furthermore, each memory cell includes a floating and a control gate. The floating and control gates are separated by a channel region.
In the nonvolatile semiconductor device having the above-mentioned structure, a data bit is programmed or erased by conditioning a predetermined voltage difference between the control gate and the channel region. With this voltage condition, electrons are injected into the floating gate from the channel region through a tunneling current. Alternatively, the electrons escape from the floating gate into the channel region. In addition, a potential at the floating gate is determined by a ratio of the capacitance between the control and floating gates and the capacitance between the floating gate and the channel region.
FIG. 1 is a circuit diagram showing a cell string in a conventional nonvolatile semiconductor memory device. Referring to FIG. 1, one end of the conventional cell string is connected to a bitline BL through a selection transistor SST, while the other end of the cell string is connected to a source line SL through the other selection transistor GST. These days, there is a high demand for semiconductor devices having high integration densities. Therefore, because the nonvolatile semiconductor memory device has a high integration density, distances between adjacent memory cells MC1˜MC32 are being reduced. Because of this reduction in the distance between adjacent memory cells, the floating gate of the memory cell attains additional significance. This additional significance exists because of the capacitance between floating and control gates of an adjacent memory cells, and also because of the capacitance between the floating gate and the channel region of the memory cell.
Referring to FIG. 1, the memory cells MC1 and MC32 are adjacent to the selection transistors GST and SST, respectively. Furthermore, the memory cells MC2 and MC31 are located at the side of memory cells MC1 and MC32 respectively. In addition, as mentioned above, the selection transistors GST and SST are located at the far ends of the string by the side of memory cells MC1 and MC32, respectively.
The selection transistors GST and SST are dissimilar from the memory cells MC1˜MC32 in terms of structure and operational characteristics. For example, the operational voltages of the selection transistors GST and SST may be different than those of memory cells MC1˜MC32. Because memory cells MC1 and MC32 are very close to the selection transistors GST and SST respectively, it may be possible that capacitive coupling between the adjacent transistors may affect the characteristics of memory cells MC1 and MC32. In particular, the characteristics of memory cells MC1 and MC32 may change to the extent that certain characteristics of memory cells MC1 and MC32 may differ from those of the other memory cells MC2˜MC31. These characteristics may include, for example, the capacitance within the memory cells.
Thus, there may be a problem in a conventional nonvolatile semiconductor memory device that the outer memory cells MC1 and MC32 adjacent to the selection transistors GST and SST respectively, operate with operating characteristics that are different from those of the other memory cells MC1˜MC31.
In addition, a conventional semiconductor device may also have a problem of insulation degradation. Particularly, on a conventional semiconductor memory device, the insulating layers between the gates of memory cells MC1, MC32 and the gates of selection transistors GST, SST may be degraded.
For example, as shown in FIG. 2, at a particular stage of programming a memory cell MC1, a word line WL1 gating the memory cell MC1 is controlled at a program voltage Vpgm (e.g., 24V), while the ground selection signal GSL is controlled at a ground voltage VSS. In this case, a large voltage gap is generated between the word line WL1 and the ground selection signal GSL, as shown in FIG. 3. This large voltage gap may cause the insulating layer between the gate G of the ground selection signal GST and the control gate CG of the memory cell MC1 to be degraded.
In addition, as shown in FIG. 4, at a particular stage of programming a memory cell MC32, a large voltage gap is generated between the word line WL32 and the string selection signal SSL. This large voltage gap may cause the insulating layer between the gate G of the string selection signal SST and the control gate CG of the memory cell MC32 to be degraded.
The present disclosure is directed towards overcoming one or more problems associated with the prior art semiconductor memory device.